1. Field of the Invention
The present invention relates generally to a semiconductor memory equipped with a serial data reading circuit, and a method of outputting serial data from a semiconductor memory. More particularly, this invention relates to an improvement which minimizes the circuit area in a semiconductor memory device like a video random access memory (VRAM).
2. Description of the Related Art
Recently, high resolution and multicolor techniques have been improved for graphics displays used in TV's, VTR's and personal computers. It is therefore demanded that a video random access memory (VRAM) should have a larger capacity, and faster and higher performances. The ever-increasing performance of VRAM's increases the circuit area in those devices, thus enlarging the devices. To avoid the undesirable enlargement of such devices, it is important to suppress the increase in circuit area on designing semiconductor memory devices.
FIG. 1 shows a block circuit of a typical VRAM. The VRAM includes a RAM (Random Access Memory) section 31 and an SAM (Serial Access Memory) section 41.
The RAM section 31 includes a memory section 32, an input circuit 33, a column address buffer 34, a row address buffer 35, a row decoder 36, a column decoder 37, a sense amplifier 38 and a RAM input/output (I/O) buffer 39.
The memory section 32, which will be discussed later in detail, includes a plurality of memory cells (not shown) arranged in a two-dimensional array. Each memory cell stores 1-bit information. The input circuit 33 receives various externally supplied signals such as a row address strobe signal/RAS, and generates various enable signals and various control signals, based on the various input signals.
The column address buffer 34 and row address buffer 35 receive externally supplied address signals A.sub.0 to A.sub.8. The row address buffer 35 latches the input address signals A.sub.0 to A.sub.8 in response to the row address strobe signal /RAS and supplies the latched address signals A.sub.0 to A.sub.8 as row address signals RA.sub.0 to RA.sub.8 to the row decoder 36. Based on the row address signals RA.sub.0 to RA.sub.8, the row decoder 36 selects one of word lines WL in the memory section 32. Data stored in individual memory cells which are connected to the selected word line WL are output on an associated pair of bit lines BL and /BL.
The column address buffer 34 latches the input address signals A.sub.0 to A.sub.8 in response to a column address strobe signal /CAS and supplies the latched address signals A.sub.0 to A.sub.8 as column address signals CA.sub.0 to CA.sub.8 to the column decoder 37. Based on the column address signals CA.sub.0 to CA.sub.8, the column decoder 37 selects one of multiple bit line pairs BL and /BL.
As a word line WL and bit line pair BL and /BL are selected, one memory cell is specified. One of data D.sub.1 to D.sub.8 can be written via the RAM I/O buffer 39 into the specified memory cell by an external device (not shown), via sense amplifier 38. Data (e.g., D.sub.1) stored in the specified memory cell can be output to an external device via the sense amplifier 38, a common bus CB and the I/O buffer 39.
The SAM section 41 includes a serial register group 42, a transfer gate group 43, a transfer controller 44, a serial address counter 45, a serial decoder 46 and a SAM I/O buffer 47.
The serial register group 42 includes a plurality of registers which are connected via the associated transfer gates to the associated bit line pairs BL and/BL of the memory section 32. The switching of the individual gates in the transfer gate group 43 is controlled by the transfer controller 44. The transfer controller 44 controls the transfer gate group 43 based on at least one of the control signals produced by the input circuit 33. Cell data stored in the memory cells which are connected to one selected word line WL are transferred via the transfer gates to the serial register group 42. The data transfer to the serial register group 42 from the memory section 32 is generally called read transfer.
The serial register group 42 can provide the memory section 32 with data, stored in its registers, via the transfer gate group 43. Individual pieces of data are stored in the memory cells which are connected to a selected one word line WL. The data transfer to the memory section 32 from the serial register group 42 is generally called write transfer.
The selection of the read transfer or write transfer is made based on the row address strobe signal /RAS and a write enable signal /WE. More specifically, when the write enable signal /WE has a high (H) level upon the falling of the row address strobe signal /RAS to a low (L) level, the read transfer mode is selected. When the write enable signal /WE has an L level upon the falling of the row address strobe signal /RAS to the L level, on the other hand, the write transfer mode is selected.
The serial address counter 45 receives the column address signals CA.sub.0 to CA.sub.8 from the column address buffer 34 and an externally supplied system clock signal SC. The counter 45 sets an initial address used for reading data from the serial register group 42, based on the column address signals CA.sub.0 to CA.sub.8. The counter 45 supplies the serial address signals SA.sub.0 to SA.sub.8 indicative of this initial address to the serial decoder 46. The counter 45 counts the number of pulses in the system clock signal SC, and outputs the serial address signals SA.sub.0 -SA.sub.8 indicating a new address which is obtained by adding the count value to the initial address. In other words, the counter 45 outputs such serial address signals SA.sub.0 -SA.sub.8 that the address value indicative of those serial address signals SA.sub.0 -SA.sub.8 is incremented by one every time one pulse of the system clock signal SC is input to the counter 45, to the serial decoder 46.
The serial decoder 46 selects a pair of bit lines BL and /BL based on the serial address signals SA.sub.0 -SA.sub.8. The register in the serial register group 42, which is connected to the selected bit line pair BL and /BL, outputs data, stored in itself, as serial output data (e.g., SD.sub.1) via the SAM I/O buffer 47.
FIG. 2 shows the memory section 32 and peripheral circuits which are coupled thereto. As shown in FIG. 2, the memory section 32 consists of two blocks 32a and 32b. A circuit section 50 is for reading output data D.sub.1 (one of eight output data D.sub.1 -D.sub.8) from the memory section 32, and includes a RAM output buffer 55 which is a part of the RAM I/O buffer 39. A circuit section 60 reads serial output data SD.sub.1 (one of eight output data SD.sub.1 -SD.sub.8) from the serial register group 42, and includes a SAM output buffer 64 which is a part of the SAM I/O buffer 47.
Each of the blocks 32a and 32b includes a memory cell array (MCA) 51, first and second sense buffers 52 and 53, and a common bus driver 54. The selection of the block 32a or the block 32b is made by the row address signal RA.sub.8. For instance, when the row address signal RA.sub.8 is at an L level, the block 32a is selected. When the row address signal RA.sub.8 is at an H level, the block 32b is selected. For the unselected block, the voltage supplied to this block is controlled down to a low potential to save the power consumption.
The common bus drivers 54 of the blocks 32a and 32b are connected via the common bus CB to the RAM output buffer 55. Data which is output from the selected block 32a or 32b is output as output data D.sub.1 to an external circuit via the common bus CB and RAM output buffer 55.
The common bus CB is connected to a P channel MOS transistor 56 for resetting the potential of the bus CB. This MOS transistor 56 has a drain connected to the common bus CB, a source connected to a high-potential power supply V.sub.CC and a gate connected to the output terminal of a NOR gate 57. The NOR gate 57 receives a reset signal RST and a control signal RTRZ. The reset signal RST is set high when the row address strobe signal /RAS has an H level. The control signal RTRZ indicates that the mode becomes the read transfer mode, and is generated by the input circuit 33 shown in FIG. 1. The input circuit 33 outputs the H-level control signal RTRZ when a data transfer signal /DT has an L level at the falling timing of the row address strobe signal /RAS. When the row address strobe signal /RAS has an H level or the mode is the read transfer mode, therefore, the potential of the common bus CB is reset to the high-potential voltage V.sub.CC.
As shown in FIG. 2, the serial register group (SRG) 42 is connected to latch type first and second sense buffers 61 and 62 which assist faster data reading.
FIG. 4 presents the detailed illustration of the serial register group 42 and its peripheral circuits. Individual registers 42a in the SRG 42 are connected via associated transfer gates 42b to a first pair of serial data bus lines SDB.sub.1 and /SDB.sub.1 or a second pair of serial data bus lines SDB.sub.2 and /SDB.sub.2. Each transfer gate 42b is constituted of an N channel MOS transistor. The serial decoder 46 controls the switching of the individual transfer gates 42b based on the serial address signals SA.sub.1 -SA.sub.8. Data stored in one of two adjoining registers 42a is transferred to the first sense buffer 61 via the first serial data bus line pair SDB.sub.1 and /SDB.sub.1, while data stored in the other register 42a is transferred to the second sense buffer 62 via the second serial data bus line pair SDB.sub.2 and /SDB.sub.2.
The first and second sense buffers 61 and 62 latch data from the registers 42a and output the latched data to a common bus driver 63 shown in FIG. 2. The common bus driver 63 receives the serial address signal SA.sub.0. When the serial address signal SA.sub.0 is set low, the common bus driver 63 outputs the data, latched in the first sense buffer 61, as serial data SD.sub.1 via the SAM output buffer 64. When the serial address signal SA.sub.0 is set high, the common bus driver 63 outputs the data, latched in the second sense buffer 62, as serial data SD.sub.1 via the SAM output buffer 64. The alternate outputting of the data latched in the first and second sense buffers 61 and 62 speeds up the data reading from the SRG 42.
To ensure fast image drawing on a graphics display, data should be read from the SRG 42 of the VRAM at a high speed. In particular, it is demanded to speed up the data reading after the read transfer to the SRG 42 from each memory cell array (MCA) 51 or shorten the time required for outputting the first data in the SRG 42 as serial data SD.sub.1 from the SAM output buffer 64.
It however takes time to transfer data to the SRG 42 from the MCA 51. If the system clock SC is supplied immediately after the read transfer, data to be read from the SRG 42 may become insufficient or data previously read may be undesirably read again.
Circuit section 60 is directed toward avoiding such uncertain data reading while speeding up the data reading process. In circuit section 60, two latch circuits 65 and 66 are provided. The first latch circuit 65 is connected between the common bus driver 63 and the first sense buffer 52 of each of the blocks 32a and 32b. The second latch circuit 66 is connected between the common bus driver 63 and the second sense buffer 53 of each block 32a or 32b. In transferring data to the SRG 42 from the MCA 51, the RAM section 31 supplies data, read according to the initial address, to the common bus driver 63 via the first or second sense buffer 52 or 53 and the latch circuit 65 or 66.
FIG. 3 shows a part of the memory section 32. The column decoder 37 selects two bit line pairs BL and /BL based on the column address signals CA.sub.1 -CA.sub.8. Data in the cells associated with the selected two bit line pairs are respectively transferred to the latch circuits 65 and 66 via the data bus line pair DB.sub.1 and /DB.sub.1, the data bus line pair DB.sub.2 and /DB.sub.2, and the first and second sense buffers 52 and 53. The latch circuits 65 and 66 latch the transferred data.
In response to the serial address signal SA.sub.0 (originating from the column address signal CA.sub.0), the common bus driver 63 for the SRG 42 selects one of the latch circuits 65 and 66 and outputs the data from the selected latch circuit as output data SD.sub.1 at the initial address.
While this output data SD.sub.1 is being output, data transfer to the SRG 42 from the MCA 51 is completed. The serial address counter 45 outputs the serial address signals SA.sub.0 -SA.sub.8, associated with a new address (initial address+1) based on the counted pulses of the clock signal SC, to the serial decoder 46.
Based on those serial address signals, the serial decoder 46 selects two registers 42a. Data in the selected two registers 42a are transferred to the sense buffers 61 and 62 via the serial data bus line pairs SDB.sub.1 and /SDB.sub.1 and SDB.sub.2 and /SDB.sub.2, respectively. The sense buffers 61 and 62 latch the transferred data.
The common bus driver 63 selects one of the sense buffers 61 and 62 in response to the serial address signal SA.sub.0, and allows the output buffer 64 to output the data from the selected sense buffer as output data SD.sub.1 at the address "initial address+1".
During the data transfer to the SRG 42 from the MCA 51, the output data SD.sub.1 at the initial address is supplied to the SAM output buffer 64 in the above manner. This scheme increases the data-reading speed immediately after data transfer with a reliability.
Since the above-discussed VRAM is designed to output 8-bit serial output data SD.sub.1 -SD.sub.8, however, the read circuit 60 which includes the latch circuits 65 and 66 is also provided for each of the other seven serial output data SD.sub.2 -SD.sub.8. This circuit design considerably increases the necessary circuit area in the VRAM chip.